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Benchmarks for interconnect parasitic resistance and capacitance

By: Cantrell, C.; Singh, A.; Bonifield, T.; Nagaraj, N.S.; Cano, F.; Balsara, P.; Kulkarni, M.; Narasimha, U.;

2003 / IEEE / 0-7695-1881-8


This item was taken from the IEEE Conference ' Benchmarks for interconnect parasitic resistance and capacitance ' Interconnect parasitics are dominating circuit performance, signal integrity and reliability in IC design. Copper/low-k process effects are becoming increasingly important to accurately model interconnect parasitics. Even if the interconnect process profile is accurately represented, approximations in parasitic extraction could cause large errors. Typically, researchers and designers have been using pre-defined set of structures to validate the accuracy of interconnect models and parasitic extraction tools. Unlike industry benchmarks on circuits such as MCNC benchmarks, no benchmarks exist for interconnect parasitics. This paper discusses the issues in accurate interconnect modeling for 130 nm and below copper/ultra low-k technologies. A set of benchmark structures that could be used to validate accuracy and compare parasitic extraction tools is proposed. Silicon results from 130 nm technology are presented to illustrate the usefulness of these benchmarks. Results of application of these benchmarks to compare parasitic extraction tools are presented to demonstrate systematic validation of resistance and capacitance extraction.