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Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D

By: Lee, B.H.; Mocuta, A.; Welser, J.; Haensch, W.; Agnello, P.; Leobandung, E.; Yang, I.Y.; Ieong, M.; Ku, S.H.; Narasimha, S.; Jenkins, K.A.; Domenicucci, A.; Gribelyuk, M.; Kermel, H.; Sendelbach, M.; Jamin, F.; Mezzapelle, J.; Mitchell, R.M.; Chakravarti, A.; Mocuta, D.; Lavoie, C.; Cabral, C.; Chan, K.; Mo, R.; O'Neil, P.; Rim, K.; Sadana, D.; Bedell, S.; Chen, H.;

2002 / IEEE / 0-7803-7462-2

Description

This item was taken from the IEEE Conference ' Performance enhancement on sub-70 nm strained silicon SOI MOSFETs on ultra-thin thermally mixed strained silicon/SiGe on insulator (TM-SGOI) substrate with raised S/D ' High quality ultra-thin TM-SGOI substrate with T/sub SOI/ < 55 nm is developed to combine the device benefits of strained silicon and SOI. 80-90% Id,sat and electron mobility increase are shown in long channel nFET device. For the first time, 20-25% device performance enhancement is demonstrated at 55 nm short channel strained silicon SGOI nFET devices.