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Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode

By: Kwong, D.L.; Niwa, M.; Harada, Y.; Clark, R.D.; Lei, X.; Lee, C.H.; Sim, J.H.; Bae, S.H.; Bai, W.P.; Lee, J.J.;

2002 / IEEE / 0-7803-7312-X

Description

This item was taken from the IEEE Conference ' Self-aligned ultra thin HfO/sub 2/ CMOS transistors with high quality CVD TaN gate electrode ' In this paper, we have demonstrated and characterized self-aligned, gate-first CVD TaN gate n- and p-MOS transistors with ultra thin (EOT=11/spl sim/12 /spl Aring/) CVD HfO/sub 2/ gate dielectrics. These transistors show no sign of gate deletion and excellent thermal stability after 1000/spl deg/C, 30 s N/sub 2/ anneal. Compared with PVD TaN devices, the CVD TaN/HfO/sub 2/ devices exhibit lower leakage current, smaller CV hysteresis, superior interface properties, higher transconductance, and superior electron and hole mobility.