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Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing

By: Tschanz, J.; De, V.; Borkar, S.; Karnik, T.; Liqiong Wei; Burns, S.; Borkar, N.; Govindarajulu, V.; Yibin Ye;

2002 / IEEE / 0-7803-7310-3

Description

This item was taken from the IEEE Conference ' Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing ' Summary form only given. Joint optimizations of dual-V/sub T/ allocation and transistor sizing reduce low-V/sub T/ usage by 36%-45% and leakage power by 20% in a high performance microprocessor, with minimal impact on total active power and die area. An enhancement of the optimum design allows processor frequency to be increased efficiently during manufacturing.