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A transition-encoded dynamic bus technique for high-performance interconnects

By: Krishnamurthy, R.; Rai, N.; Anders, M.; Borkar, S.;

2002 / IEEE / 0-7803-7310-3

Description

This item was taken from the IEEE Conference ' A transition-encoded dynamic bus technique for high-performance interconnects ' Summary form only given. A transition-encoded dynamic bus technique enables interconnect delay reduction while maintaining the robustness and switching energy behavior of a static bus. Efficient circuits, designed for a drop-in replacement, enable significant delay and peak-current reduction even for short buses, while obtaining energy savings at aggressive delay targets. In a 180 nm 32-bit microprocessor, 79% of all global buses exhibit 10%-35% performance improvement with this technique.