Use this resource - and many more! - in your textbook!
AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors
By: Yibin Ye; Karnik, T.; Borkar, S.; De, V.; Govindarajulu, V.; Burns, S.; Liqiong Wei; Tschanz, J.;
2002 / IEEE / 1-58113-461-4
This item was taken from the IEEE Conference ' Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors ' We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5/spl times/ larger computation runtime than iSTATS due to its iterative nature.
High Performance Microprocessors
Lagrangian Relaxation Based Tool
Heuristic Iterative Optimization Flow
Cmos Logic Circuits
Simultaneous Dual-vt Allocation
Total Power Optimization
Integrated Circuit Design
Design Automation Solutions