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ASIC wafer test system for the ATLAS Semiconductor Tracker front-end chip

By: Cosgrove, D.; Fadeyev, V.; Ciocio, A.; Busek, N.; Bialas, W.; Anghinolfi, F.; Zetti, F.; Yaver, H.; Wilder, M.; Vu, C.; Stezelberger, T.; Spieler, H.; Rosenbaum, F.; Pritchard, T.; Niggli, H.; Murray, W.; Lacasta, C.; Kaplon, J.; Haber, C.; Grillo, A.A.; Gilchriese, M.; Flacco, C.;

2001 / IEEE / 0-7803-7324-3


This item was taken from the IEEE Conference ' ASIC wafer test system for the ATLAS Semiconductor Tracker front-end chip ' An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented.