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Deep-submicron CMOS process integration of HfO/sub 2/ gate dielectric with poly-si gate

By: Chang-Seok Kang; Rino Choi; Onishi, K.; Chenming Hu; Tsu-Jae King; Takeuchi, H.; Lin, R.; Qiang Lu; Lee, J.C.;

2001 / IEEE / 0-7803-7432-0

Description

This item was taken from the IEEE Conference ' Deep-submicron CMOS process integration of HfO/sub 2/ gate dielectric with poly-si gate ' We demonstrate the integration of sputterdeposited ultra-thin HfO2 gate dielectric into a sub-100 nm gate length CMOS process using poly-Si as the gate material. Good device characteristics have been observed down to 70 nm physical gate length, and an equivalent gate oxide thickness (EOT) of 11�has been achieved. Both p-FETs and n-FETs with HfO2 gate dielectric show ~104 times lower gate leakage than Si02 with comparable EOT. Data and model suggest that the gate leakage of Hf02 will be lOO times lower than that of Si02 down to 5�EOT.