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Integration of high-k gate stack systems into planar CMOS process flows

By: Huff, H.R.; Agarwal, A.; Jackson, M.D.; Torres, K.; Murto, R.W.; Gutt, J.; Gardner, M.I.; Larson, L.A.; Bergmann, R.; Derro, D.J.; Borthakur, S.; Alshareef, H.; Lim, C.; Hou, A.; Shaapur, F.; Foran, B.; Young, C.; Brown, G.A.; Zeitzoff, P.; Bersuker, G.; Lim, S.; Lim, J.E.; Nguyen, B.; Kim, Y.; Perrymore, L.; Riley, D.; Barnett, J.; Sparks, C.; Freiler, M.; Gebara, G.; Bowers, B.; Chen, P.J.; Lysaght, P.;

2001 / IEEE / 4-89114-021-6

Description

This item was taken from the IEEE Conference ' Integration of high-k gate stack systems into planar CMOS process flows ' We review several gate stack fabrication issues critical for robust, commercially viable tools, including assessment of possible fab contamination due to the higher-k gate dielectrics and the role of subsequent thermal procedures during, for example, source/drain anneals (including the importance of the oxygen partial pressure) to ensure their compatibility with conventional planar polysilicon CMOS transistor fabrication processes.