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An algorithm for bi-decomposition of logic functions
2001 / IEEE / 1-58113-297-2
This item was taken from the IEEE Conference ' An algorithm for bi-decomposition of logic functions ' We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal don't-cares during the decomposition to produce compact well-balanced netlists with short delay. The resulting netlists are provably nonredundant and facilitate test pattern generation. Experimental results over MCNC benchmarks show that our approach outperforms SIS and other BDD-based decomposition methods in terms of area and delay of the resulting circuits with comparable CPU time.
Multi-output Incompletely Specified Logic Functions
Test Pattern Generation
Test Pattern Generators
Automatic Test Pattern Generation
Binary Decision Diagrams
Two-input Logic Gates