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A 0.11 /spl mu/m CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores

By: Kadomura, S.; Nagashima, N.; Uematsu, M.; Yamamura, I.; Nagano, T.; Kawano, M.; Takao, Y.; Yamaguchi, S.; Kotani, Y.; Mitani, J.; Kudo, H.; Yoshie, K.;

2000 / IEEE / 0-7803-6438-4

Description

This item was taken from the IEEE Conference ' A 0.11 /spl mu/m CMOS technology with copper and very-low-k interconnects for high-performance system-on-a-chip cores ' This paper describes a 0.11 /spl mu/m CMOS technology with high-reliable copper and very-low-k (VLK) (k<2.7) interconnects for high performance and low power applications. Aggressive design rules, 0.11 /spl mu/m gate transistor, and 2.2 /spl mu/m/sup 2/ 6T-SRAM cell are realized by using KrF 248 nm lithography, optical proximity-effect correction (OPC), and gate-shrink techniques. Drain current of 0.63 mA//spl mu/m and 0.28 mA//spl mu/m are realized for nMOSFET and pMOSFET with 0.11 /spl mu/m gate, respectively. Propagation delay of 2-input NAND with the copper/hybrid VLK interconnects is estimated. The delay is improved by more than 70%, compared to 0.18 /spl mu/m CMOS technology with copper/FSG interconnects.