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A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs

By: Ha, D.W.; Lee, J.W.; Kwak, D.W.; Hwang, Y.S.; Shin, D.W.; Koh, G.H.; Lee, K.H.; Jeong, G.T.; Park, Y.W.; Moon, J.T.; Jeong, H.S.; Chung, T.Y.; Kim, K.N.; Uh, H.S.; Lee, S.H.; Lee, J.G.; Oh, J.H.; Park, B.J.; Lee, J.K.; Chun, Y.S.; Lee, M.H.; Shin, S.H.;

2000 / IEEE / 0-7803-6305-1

Description

This item was taken from the IEEE Conference ' A 0.13 /spl mu/m DRAM technology for giga bit density stand-alone and embedded DRAMs ' In this paper, a 0.13 /spl mu/m DRAM technology is developed with KrF lithography. In order to extend KrF lithography to 0.13 /spl mu/m generation, full CMP technology is developed in order to provide flat surface. Full self-aligned contact (SAC) technology can make memory cell processes easy because memory cell landing pads and storage node contact plug can be formed with self-aligned manner respect to word-line and bit-line. By these technologies, the extremely small memory cell is easily realized without any yield loss. Low-temperature PAOCS MIS capacitor with Al/sub 2/O/sub 3/ can greatly reduce the aspect ratio of metal contact, thereby yielding stable metal contact process. And it can help DRAM technology easily to merge with logic process. The 0.13 /spl mu/m integration technology is successfully demonstrated with 1 Gb DRAM.