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The impact of Cu/low /spl kappa/ on chip performance

By: Zarkesh-Ha, P.; Meindl, J.D.; JinJoo Lee; Loh, W.; Bendix, P.;

1999 / IEEE / 0-7803-5632-2

Description

This item was taken from the IEEE Conference ' The impact of Cu/low /spl kappa/ on chip performance ' A new model to predict percentage of performance improvement using copper and/or low /spl kappa/ is rigorously derived. Based on the new model, it is shown that for a typical ASIC design in 0.25 /spl mu/m technology, using copper interconnect alone can improve the speed by about 10%; however in the same technology, using low /spl kappa/ dielectric (/spl epsi//sub r/=2.5) alone can improve the speed by about 27%. The new model indicates that the performance gain for copper and low /spl kappa/ are not additive. Finally, the model is applied to the NTRS projections to explore the performance gain through future technology generations.