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Future perspective and scaling down roadmap for RF CMOS
By: Momose, H.S.; Morifuji, E.; Iwai, H.; Katsumata, Y.; Kinugawa, M.; Matsuoka, F.; Kimijima, H.; Yoshitomi, T.; Ohguro, T.;
1999 / IEEE / 4-930813-93-X
This item was taken from the IEEE Conference ' Future perspective and scaling down roadmap for RF CMOS ' The concept of future scaling-down for RF CMOS technology has been investigated in terms of f/sub T/, f/sub max/, RF noise, linearity, and matching characteristics, based on simulation and experiments. It has been found that gate width and finger length are key parameters, especially in sub-100 nm gate length generations.
Cmos Logic Circuits
Integrated Circuit Noise
Field Effect Mmic
Integrated Circuit Design
Cmos Integrated Circuits
Integrated Circuit Testing
Rf Cmos Technology