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The X-MatchLITE FPGA-based data compressor

By: Feregrino, C.; Nunez, J.L.; Jones, S.; Bateman, S.;

1999 / IEEE / 0-7695-0321-7


This item was taken from the IEEE Conference ' The X-MatchLITE FPGA-based data compressor ' This paper introduces a hardware amenable algorithm for lossless data compression and a highly integrable architecture which enables Gbit/s compression using contemporary ASIC technology. An FPGA prototype of the architecture is presented. A comparison between this prototype and the full version of the system is made together with the details of the engineering decisions needed to successfully realize an ASIC compressor in FPGA technology.