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Process integration of a direct-on-metal, non-etchback, /spl kappa/=2.5 spin-on polymer for the 0.18 /spl mu/m CMOS technology node
By: Hacker, N.P.; Dunne, J.; Treadwell, C.A.; Kavari, R.; MacInnes, L.M.; Figge, L.K.; Ma, S.; Ray, G.W.; Sum, J.C.; Hendricks, N.;
1999 / IEEE / 0-7803-5174-6
This item was taken from the IEEE Conference ' Process integration of a direct-on-metal, non-etchback, /spl kappa/=2.5 spin-on polymer for the 0.18 /spl mu/m CMOS technology node ' Process integration of a /spl kappa/=2.5 spin-on dielectric polymer into double-level metal CMOS parametric test structures at two technology nodes (0.35 /spl mu/m and 0.18 /spl mu/m) is described. This was accomplished using a single-coat, DOM (direct-on-metal), NEB (nonetchback) process. The structures are globally planarized using a standard CMP process on an oxide-based layer used to cap the low-k spin-on dielectric. Details of the process are presented together with electrical data demonstrating very low capacitance and low leakage current, even after multiple thermal cycles.
Cmos Technology Node
Spin-on Dielectric Polymer
Double-level Metal Cmos Parametric Test Structures
Single-coat Direct-on-metal Nonetchback Process
Single-coat Dom Neb Process
Globally Planarized Structures
Standard Cmp Process
Oxide-based Cap Layer
Low-k Spin-on Dielectric
Multiple Thermal Cycles
Dielectric Thin Films
Chemical Mechanical Polishing
Integrated Circuit Manufacture
Integrated Circuit Metallisation
Integrated Circuit Interconnections
Cmos Integrated Circuits
Integrated Circuit Testing
Direct-on-metal Nonetchback Spin-on Polymer