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Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect

By: Cochet, M.; Assous, M.; Roman, A.; Tabone, C.; Morand, Y.; Berruyer, P.; Demolliens, O.; Renaud, D.; Trouillet, Y.; Beverina, A.; Tardif, F.; Sicurani, E.; Ulmer, L.; Mourier, T.; Morel, T.; Cordeau, M.; Moussavi, M.; Jourdan, F.; Passemard, G.; Gobil, Y.; Lajoinie, E.; Arvet, C.; Louis, D.; Tabouret, E.; Blanc, R.; Feldis, H.;

1999 / IEEE / 0-7803-5174-6

Description

This item was taken from the IEEE Conference ' Copper-SilK integration in a 0.18 /spl mu/m double level metal interconnect ' This paper describes the integration of copper and SilK in a 0.18 /spl mu/m DLM interconnect. The main integration issues such as dual damascene patterning, SilK porosity and copper filling have been addressed, as shown by the 0.5 /spl Omega/-100% yield obtained for 0.3 /spl mu/m vias. The Cu/SilK interest is confirmed by a 40% RC reduction compared to a Cu-SiO/sub 2/ structure.