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Development of three-dimensional memory die stack packages using polymer insulated sidewall technique

By: Kim, J.S.; Hyoung-Soo Ko; Paik, K.W.; Cho, S.D.; Jang, S.Y.; Yoon, H.G.;

1999 / IEEE / 0-7803-5231-9

Description

This item was taken from the IEEE Conference ' Development of three-dimensional memory die stack packages using polymer insulated sidewall technique ' A novel design of three dimensional (3D) memory die stack package has been established. The prototype of the 3D package using mechanical dies has been demonstrated. The whole processes of fabricating the 3D package consists of wafer cutting into die segments, die passivation including sidewall insulation of dies, via opening on the original I/O pads, I/O redistribution from center pads to sidewall, bare die stacking using polymer adhesives, sidewall interconnection and solder balls attachment. There are several remarkable improvements in this 3D package design compared with the currently available 3D packages. The most unique feature of this newly developed package design is the sidewall insulation prior to the I/O redistribution, which produces (1) better chip-to-wafer yield and (2) significant process simplification in the following fabrication steps. According to this design, 100% of dies on a conventional wafer can be used without any neighboring die loss, which may be caused by the I/O redistribution process of conventional 3D package design. Furthermore this newly developed 3D bare die stack package design can simplify the following processes such as I/O redistribution, sidewall insulation, sidewall interconnection, and package formation. The mechanical integrity of the prototype 3D stacked package meets the JEDEC Level III and 85/spl deg/C/85% test.