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Circuit performance variability decomposition

By: Spanos, C.; Orshansky, M.; Chenming Hu;

1999 / IEEE / 0-7803-5154-1


This item was taken from the IEEE Conference ' Circuit performance variability decomposition ' In this paper, circuit performance variability composition is analyzed. Traditionally, the device variability has been the dominant source. It is believed that with continuing technology scaling into the deep sub-micron regime, the interconnect constitutes an increasing portion of the overall circuit delay, and variability. In this paper, we analytically investigate the delay variability composition for an advanced 0.18 /spl mu/m CMOS technology, accounting for the significant intra-field variability. A more realistic model to estimate the variance of global interconnect lines is proposed. The results indicate that the device variability of good designs contributes about 90% of the overall variability.