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Analysis of snapback behavior on the ESD capability of sub-0.20 /spl mu/m NMOS

By: Ramaswamy, S.; Vasanth, K.; Gupta, V.; Amerasekera, A.;

1999 / IEEE / 0-7803-5220-3

Description

This item was taken from the IEEE Conference ' Analysis of snapback behavior on the ESD capability of sub-0.20 /spl mu/m NMOS ' The self-biased lateral NPN (LNPN) operation of NMOSFETs is analyzed and the requirements to support high injection currents are determined. The effects of process design and scaling on the LNPN behavior are investigated using analytical methods as well as device simulations and experimental data from three technologies with feature sizes of 0.13 /spl mu/m, 0.18 /spl mu/m, and 0.25 /spl mu/m. Specifically, the influence of gate oxides <30 /spl Aring/, and the effects of CoSi/sub 2/ and TiSi/sub 2/ are characterized with the purpose of defining process dependencies and design space. It is shown that as gate oxides get thinner, oxide breakdown may become a limiting factor depending on the LNPN properties. Furthermore, changes in LNPN current gain through process or design variations, and the substrate resistance, can be used to tune ESD performance. Hence, transistor design and process choices can be made to ensure that the LNPN is optimized for successful operation even for very thin gate oxides in sub-0.2 /spl mu/m technologies.