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A 940 MHz data rate 8 Mb CMOS SRAM

By: Burns, S.; Hall, S.; Robillard, M.; Frederick, T.; Graf, M.; Conner, J.; Roberts, A.; Braceras, G.; Wistort, R.;

1999 / IEEE / 0-7803-5126-6

Description

This item was taken from the IEEE Conference ' A 940 MHz data rate 8 Mb CMOS SRAM ' An 8 Mb CMOS SRAM cycles at 470 MHz and provides a data rate of 940 MHz when run in the double-data rate (DDR) mode. Improved redundancy minimizes SRAM latency, enabling 3.4 ns access time. The HSTL I/O performance is enhanced by using flip-chip C4 packaging and by decoupling the I/O supply on-chip. The 8 Mb SRAM has an architecture to allow both /spl times/18 and /spl times/36 organizations, as well as a 4 Mb cut-down.