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Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond
By: Nakajima, K.; Azuma, A.; Hiura, Y.; Kohyama, Y.; Suguro, K.; Akasaka, Y.; Toyoshima, Y.; Tsuchida, K.; Honjo, A.; Nitta, H.; Miyano, K.;
1998 / IEEE / 0-7803-4774-9
This item was taken from the IEEE Conference ' Integration technology of polymetal (W/WSiN/Poly-Si) dual gate CMOS for 1 Gbit DRAMs and beyond ' Integration technology of low resistance word line and scaled CMOSFETs for 1 Gbit DRAMs and beyond is proposed. Polymetal (W/WSiN/Poly-Si) word lines and dual gate CMOS FETs with oxynitride gate dielectric were introduced to the 8F/sup 2/ DRAM cell technology. Low sheet resistance of 4.5 /spl Omega///spl square/ word line with 40 nm thick W and high performance dual gate 0.18 /spl mu/m CMOS were successfully integrated without any constraint.
Random Access Memory
Ultra Large Scale Integration
Polymetal W/wsin/poly-si Dual Gate
Integrated Circuit Metallisation
Cmos Memory Circuits