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Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time
By: Sakoh, T.; Takaishi, Y.; Komuro, M.; Sakao, M.; Yoshida, K.; Okonogi, K.; Saino, K.; Horiba, S.; Koyama, K.;
1998 / IEEE / 0-7803-4774-9
This item was taken from the IEEE Conference ' Control of trench sidewall stress in bias ECR-CVD oxide-filled STI for enhanced DRAM data retention time ' This is the first detailed study of data retention characteristics of DRAM with bias ECR-CVD oxide-filled shallow trench isolation (STI). It clarifies the relationship between trench sidewall stress and data retention characteristics. Excessive stress on trench sidewalls causes strain and defect-related leakage current, and it degrades data retention time. Strain and defects are introduced by process conditions like deep trenching, high-temperature densification, and vertically etched trenching in bias ECR-CVD oxide-filled trench case. By eliminating the cause of leakage current, fully operating 0.18 /spl mu/m-rule DRAMs have been manufactured.
Data Retention Time
Defect-related Leakage Current
Vertically Etched Trenching
Random Access Memory
Trench Sidewall Stress
Integrated Circuit Reliability
Bias Ecr-cvd Oxide-filled Sti