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A manufacturable shallow trench isolation process for 0.18 /spl mu/m and beyond-optimization, stress reduction and electrical performance

By: Sur, H.; Laparra, O.; Nouri, F.; Manley, M.; Pramanik, D.; Tai, G.C.;

1998 / IEEE / 0-7803-4380-8

Description

This item was taken from the IEEE Conference ' A manufacturable shallow trench isolation process for 0.18 /spl mu/m and beyond-optimization, stress reduction and electrical performance ' An integrated shallow trench isolation process utilizing HDP (high density plasma) oxide and a highly manufacturable corner oxidation is described. The choice of trench corner oxidation temperature is shown to be critical in reducing silicon stress, and hence junction leakage, to the levels required by multi-million gate designs. This STI process is shown to be extremely robust and manufacturable. Optimal design of the trench depth and well profiles is shown to provide well-edge isolation adequate for sub-0.18 /spl mu/m technologies.