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Integration and reliability issues for low capacitance air-gap interconnect structures

By: Shieh, B.P.; Bassman, L.C.; Kim, D.-K.; Saraswat, K.C.; Ting, L.; McVittie, J.P.; List, R.S.; Nag, S.; Deal, M.D.;

1998 / IEEE / 0-7803-4285-2

Description

This item was taken from the IEEE Conference ' Integration and reliability issues for low capacitance air-gap interconnect structures ' As IC technology scales, the performance of ULSI chips is increasingly limited by the capacitance of the interconnects. The interconnect capacitance contributes to RC delay, AC power (CV/sub 2/f), and crosstalk. The use of air-gaps formed between metal lines during SiO/sub 2/ deposition has been shown to reduce the capacitance of tightly spaced interconnects by as much as 40% compared to homogeneous SiO/sub 2/ (Shieh et al, IEEE Electron Dev. Lett. vol. 19, no. 1, pp. 16-18). This capacitance reduction is comparable to, if not better than, the reduction obtained using low-k materials such as polymers in a homogeneous scheme. Air-gap formation, modeled here using the Stanford SPEEDIE deposition simulator, reduces capacitance for varying feature sizes. However, as with all low-k materials and schemes, a number of process integration and reliability issues must be addressed before air-gaps can be fully incorporated into high performance ULSI interconnects. In this paper, we present and address a number of these issues using a variety of simulation tools and experimental results. Air-gap formation has been simulated using SPEEDIE and resulting geometry input to MARC, a finite element code to simulate electromigration reliability. ANSYS, another finite element code, was used to simulate the thermal performance of interconnect stacks using air-gaps.