Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

A manufacturable embedded fluorinated SiO/sub 2/ for advanced 0.25 /spl mu/m CMOS VLSI multilevel interconnect applications

By: Pai, C.S.; Tsubokura, F.; Lindenberger, W.S.; Lai, W.Y.-C.; Cheung, K.P.; Baumann, F.H.; Chang, C.P.; Liu, C.T.; Liu, R.; Diodato, P.W.; Colonell, J.I.; Vaidya, H.; Vitkavage, S.C.; Clemens, J.T.; Velaga, A.N.;

1998 / IEEE / 0-7803-4285-2

Description

This item was taken from the IEEE Conference ' A manufacturable embedded fluorinated SiO/sub 2/ for advanced 0.25 /spl mu/m CMOS VLSI multilevel interconnect applications ' We have integrated fluorinated SiO/sub 2/ (F-SiO/sub 2/) films with k=3.5 deposited using HDP-CVD into a 0.25 /spl mu/m CMOS process. The significance of this process is that the deposition tool (HDP-CVD) and the processing step (gap fill) are identical to the reference process. We simply replace deposition of undoped SiO/sub 2/ (k=4.0) in HDP-CVD for gap fill with deposition of F-SiO/sub 2/. We have optimized the HDP-CVD process for stable F-SiO/sub 2/ films. The interlevel dielectric (ILD) is composed of HDP-CVD oxide for gap fill and PETEOS for capping before CMP planarization. This ILD structure uses F-SiO/sub 2/ embedded between metal lines. We have compared electrical results obtained from wafers processed using three-level metal 0.25 /spl mu/m CMOS technology with embedded F-SiO/sub 2/ ILD. Results obtained from contact resistance, contact yields and CMOS transistor characteristics are comparable. Moreover, FN stress results show that the gate oxide of NMOS devices has less damage for the F-SiO/sub 2/ split. We have obtained 11% capacitance reduction when comparing embedded F-SiO/sub 2/ to SiO/sub 2/ using metal comb capacitors. The effectiveness of this low k material in circuit performance is also demonstrated. Without optimizing the layout to maximize the benefits of using low k dielectrics in interconnects, the propagation delay of an 88-stage gate array shows 2.5% improvement using embedded F-SiO/sub 2/ as ILD.