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A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock

By: Abiko, H.; Fukaishi, M.; Nakamura, K.; Yotsuyanagi, M.; Matsumoto, A.;

1998 / IEEE / 0-7803-4766-8

Description

This item was taken from the IEEE Conference ' A 6 Gbps CMOS phase detecting DEMUX module using half-frequency clock ' We developed a new phase detector which can perform 1:2 data demultiplexing function. A newly developed pulse compensation technique enables one to output the analog phase difference for a half-frequency clock. This circuit can be used as both a phase detector for a PLL clock recovery circuit (CRC) and a root module for an asynchronous tree-type DEMUX. Using a new combined CRC-DEMUX structure, we achieved 6 Gbps 1:8 DEMUX with CRC using a 0.18 /spl mu/m CMOS in 83 mW power consumption.