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A new mode of hot carrier degradation in 0.18 /spl mu/m CMOS technologies

By: Clemens, J.T.; Vaidya, H.; Pai, C.S.; Liu, R.; Lai, W.Y.C.; Liu, C.T.; Cheung, K.P.; Chang, C.P.; Lloyd, E.J.; Colonell, J.I.;

1998 / IEEE / 0-7803-4770-6

Description

This item was taken from the IEEE Conference ' A new mode of hot carrier degradation in 0.18 /spl mu/m CMOS technologies ' In contrast to previous generations, we find that 0.18 /spl mu/m CMOS technologies exhibit completely different hot carrier degradation in both NMOS and PMOS devices. In addition to their smaller dimensions, the difference arises from high electric fields due to aggressive device designs for high current drives (I/sub on/). The high fields give rise to much more efficient impact-ionization and generate hot-holes which become dominant in the hot-carrier degradation, in contrast to the hot-electron injection in the previous generations. Therefore, it is essential to reduce hole trapping in thin gate oxides in order to improve the device lifetimes. We demonstrate that gate oxides grown on nitrogen ion-implanted (N I/I) Si substrates can significantly reduce hole trapping and the amount of degradation. Also, there exists a limit of the maximum power supply voltage (V/sub DD,max/) for reliable circuit operations. While aggressive device designs are commonly adopted to optimize I/sub on/, our results show that V/sub DD,max/ actually goes down almost linearly with the increase of I/sub on/ for the 0.18 /spl mu/m technologies.