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Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay

By: De, H.; Veeraraghavan, S.; O'Meara, D.; Dyer, D.; Yuan, C.; Lii, T.; Collins, S.; Reid, K.; Bhat, N.; Misra, V.; Woodruff, R.; Anderson, S.G.H.; Pettinato, C.; Gilbert, P.; Yang, I.Y.;

1998 / IEEE / 0-7803-4770-6

Description

This item was taken from the IEEE Conference ' Optimization of a 0.18 /spl mu/m 1.5 V CMOS technology to achieve 15 ps gate delay ' Summary form only given. A high performance 0.18 /spl mu/m CMOS technology with minimum 0.1 and nominal 0.13 /spl mu/m poly gate, physical 3 nm gate oxide, and 0.18 /spl mu/m local interconnect features operating at 1.5 V supply voltage is described with emphasis on the reduction of parasitic capacitances and resistances while maintaining high drive currents and low leakage currents to achieve a 15 ps unloaded ring oscillator delay. Coupling capacitance between gate and local interconnect is also discussed as a function of technology scaling as is 3 nm gate oxide reliability.