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A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs

By: Fujisaki, Y.; Kumihashi, T.; Torii, K.; Kisu, T.; Yokoyama, N.; Shoji, K.; Kachi, T.; Yamashita, H.;

1998 / IEEE / 0-7803-4770-6

Description

This item was taken from the IEEE Conference ' A scalable single-transistor/single-capacitor memory cell structure characterized by an angled-capacitor layout for megabit FeRAMs ' A single-transistor/single-capacitor ferroelectric random access memory (FeRAM) cell having a cell size of 4.5 /spl mu/m/sup 2/ has been developed using 0.5-/spl mu/m technology. This cell features a stacked capacitor structure with a poly-Si plug and an angled-capacitor layout. This unique capacitor layout increases the alignment tolerance between the plate contact and the individual capacitor electrodes without increasing the cell area. O/sub 2/ annealing was applied after the plate-contact formation to restore the remanent polarization degradation. Favorable ferroelectric capacitor characteristics were observed when this cell was used in an experimental 4-Kbit memory-cell array.