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A 0.18 /spl mu/m fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation
1998 / IEEE / 0-7803-4770-6
This item was taken from the IEEE Conference ' A 0.18 /spl mu/m fully depleted CMOS on 30 nm thick SOI for sub-1.0 V operation ' A process has been developed for fabricating 0.18 /spl mu/m CMOS devices that have excellent performance at low voltage. It uses fully depleted SOI technology. To suppress degradation of subthreshold slope due to the short channel effect, the SOI film is drastically thinned to 30 nm. An ultra-thin cobalt silicide layer efficiently reduces the high parasitic source/drain resistance that occurs with thin SOI film. The fabricated devices, which keep a subthreshold slope of less than 70 mV/decade, have a switching speed more than 1.5 times faster than that of bulk CMOS devices, when the supply voltage is 1.0 V or less.
Low Voltage Performance
Short Channel Effect
Parasitic Source/drain Resistance
Thin Film Devices
Subthreshold Slope Degradation
Fully Depleted Cmos
Semiconductor Device Reliability
Fully Depleted Soi Technology