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Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology

By: Colonell, J.I.; Cirelli, R.; Frei, M.; Gruensfelder, C.; Jacobson, D.C.; Key, R.W.; Klemens, F.P.; Lai, W.Y.C.; Lee, J.T.-C.; Liu, C.T.; Liu, R.; Oh, M.; Maynard, H.L.; Monroe, D.P.; Nalamasu, O.; Pai, C.S.; Santiesteban, R.; Silverman, P.J.; Tai, W.W.; Timko, A.; Vuong, H.; Watson, G.P.; Thoma, M.J.; Clemens, J.T.; Hillenius, S.J.; Frackoviak, J.; Cheung, K.P.; Chang, C.P.; Bolan, K.; Boulin, D.M.; Hobler, G.; Mansfield, W.; Vaidya, H.; Kuehne, S.; Bevk, J.;

1998 / IEEE / 0-7803-4770-6


This item was taken from the IEEE Conference ' Buried ultra-low-energy gate implants for sub-0.25 micron CMOS technology ' Summary form only given. We have demonstrated that the threshold voltage shifts in closely spaced, dual-poly CMOS devices are virtually eliminated by using buried, low energy gate implants. The reduced thermal budget for gate activation, made possible by short diffusion distances, not only reduces dopant lateral diffusion in the gates but also in the device channel regions. Moreover, the process allows the use of thinner gate oxides and shallower junctions and improves the control of L/sub eff/.