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A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM
By: Lee, K.H.; Sim, J.H.; Yang, W.S.; Jeong, H.S.; Cho, C.H.; Jeong, G.T.; Koh, G.H.; Kim, K.N.; Lee, J.G.; Park, B.J.; Lee, J.-G.; Bae, J.S.; Ha, D.W.;
1998 / IEEE / 0-7803-4770-6
This item was taken from the IEEE Conference ' A 0.15 /spl mu/m DRAM technology node for 4 Gb DRAM ' The DRAM process technology has been on the leading edge of semiconductor technology, and the density of DRAM has been quadrupled every three years. 1 Gb DRAM based on the 0.18 /spl mu/m technology node (generation) was successfully manufactured and much attention is now given to the process technology for 4 Gb DRAM based on 0.15 /spl mu/m technology node or smaller than 0.15 /spl mu/m technology node. 0.15 /spl mu/m technology node is considered to be transition node between 0.18 /spl mu/m which KrF lithography is used on 200 mm wafers and 0.13 /spl mu/m node in which ArF lithography will be used on 300 mm wafers. In this paper, key process and integration technologies for 0.15 /spl mu/m DRAM technology node are developed in order to satisfy both 0.18 /spl mu/m technology node and 0.13 /spl mu/m node. The process and integration technologies employed in 0.15 /spl mu/m technology node are verified with an experimental 16 Mb DRAM.
Cmos Logic Circuits
Random Access Memory
Dram Technology Node
Integrated Circuit Technology