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A 667 MHz RISC microprocessor containing a 6.0 ns 64 b integer multiplier
By: Jain, A.; Bannon, P.; Carlson, D.; Kim, S.J.; Kim, K.-I.; Hwang, G.C.; Park, S.-B.; Kobayashi, S.; Kobayashi, H.; Chen, A.; Saito, Y.; Yalala, V.; Olesin, A.; Nagarajan, M.; Mueller, R.; Miller, B.; Mehta, S.; Lilly, B.; Castelino, R.; Brasili, D.; Bouchard, G.; Blake-Campos, R.; Bertone, M.; Benninghoff, T.;
1998 / IEEE / 0-7803-4344-1
This item was taken from the IEEE Conference ' A 667 MHz RISC microprocessor containing a 6.0 ns 64 b integer multiplier ' This microprocessor is optimized for the desktop. The chip contains architectural, circuit, and technology enhancements that include a 32 kB, 2-way set associative virtual instruction cache, a 16 kB, dual-read-ported, physical data cache, and advanced branch prediction. Circuit enhancements include a 6.0 ns integer multiplier, a 19.5 ns floating-point divider, and to support low jitter, 50% duty cycle 667 MHz clock, and an on-chip PLL. The 5.7M transistor microprocessor is fabricated in a 2.0 V, 0.28 /spl mu/m CMOS process with 4-layers of metal for interconnect, measures 1.0 cm/sup 2/, and supports a 2.5 V interface.
Integrated Circuit Interconnections
Solid State Circuits
Reduced Instruction Set Computing
Dual-read-ported Physical Data Cache
Associative Virtual Instruction Cache
Cmos Digital Integrated Circuits