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A 100 Mb/s CMOS 100Base-T4 Fast Ethernet transceiver for category 3, 4 and 5 UTP
By: Samueli, H.; Yousefi, N.; Tran, H.; Lu, F.; Kruse, D.; Berman, M.; Chan, K.;
1998 / IEEE / 0-7803-4344-1
This item was taken from the IEEE Conference ' A 100 Mb/s CMOS 100Base-T4 Fast Ethernet transceiver for category 3, 4 and 5 UTP ' A 100Base-T4 Fast Ethernet transceiver based on a DSP approach supports 100 Mb/s over low-grade CAT3 unshielded twisted pair (UTP) as well as higher grade CAT4 and 5 UTP. The transceiver performs all the required physical layer (PHY) interface functions from the media-independent interface (MII) to filterless magnetic module in a single CMOS chip.
Physical Layer Interface
Filterless Magnetic Module
Bit Error Rate
100base-t4 Fast Ethernet Transceiver
Cmos Digital Integrated Circuits
Unshielded Twisted Pair