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Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 /spl mu/m CMOS technology
1997 / IEEE / 0-7803-4100-7
This item was taken from the IEEE Conference ' Gate-workfunction engineering using poly-(Si,Ge) for high-performance 0.18 /spl mu/m CMOS technology ' We show that poly-SiGe can be readily integrated as a gate material into an existing CMOS technology to achieve significant increase in the transistor performance. In order to preserve the standard salicidation scheme, a buffer poly-Si layer is introduced in the gate stack. PMOST channel profiles are optimized to account for the change of the gate workfunction. High-performance CMOS 0.18 /spl mu/m devices are manufactured using p- and n-type poly-Si/Si/sub 0.8/Ge/sub 0.2/ gates.
Buffer Poly-si Layer
Pmost Channel Profile
Semiconductor Device Doping
Gate Workfunction Engineering
Si-si/sub 0.8/ge/sub 0.2/
Cmos Integrated Circuits