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A Novel nm-grain Poly-si Gate Structure For Reduction Of Cell To Cell Write/erase Tunnel Current Deviation In High Speed Quarter Micron FLASH Memories

By: Yugami, J.; Mine, T.;

1997 / IEEE / 4-930813-75-1

Description

This item was taken from the IEEE Conference ' A Novel nm-grain Poly-si Gate Structure For Reduction Of Cell To Cell Write/erase Tunnel Current Deviation In High Speed Quarter Micron FLASH Memories '

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Engineering