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ArchMDSP: using DSPs for parallel image processing

By: Mucheroni, M.L.; Saito, J.H.; Moron, C.E.;

1997 / IEEE / 0-8186-8129-2

Description

This item was taken from the IEEE Periodical ' ArchMDSP: using DSPs for parallel image processing ' Presents a parallel machine implemented with digital signal processors (DSPs), and its corresponding programming environment. This machine, named ""Architecture using Multiple DSPs"" (ArchMDSP), is supported by a parallel environment. Images are initially mapped to the parallel system to analyse the potential of this approach, but other applications have also been analysed, including real-time and fault-tolerant problems. The mapping system makes sub-image distribution available, one sub-image for each processor. The potential offered by this architecture was analysed for image processing by certain types of operators. The host computer is a Sun SparcStation whose Sbus has a link with a multiple-module carrier card with TMS320C40 processors in a pipeline structure, where each module has 8 MBytes of memory. Timing measurements, including communication overhead and speed-up, were taken for different sizes of images.