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A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching

By: Fujisaki, Y.; Sakata, K.; Kure, T.; Yokoyama, N.; Tanaka, T.; Itoga, T.; Gotoh, Y.; Ohkura, M.; Kawakami, H.; Morimoto, T.; Kumihashi, T.; Torri, K.; Kaga, T.; Kisu, T.; Yamashita, H.; Moniwa, M.; Shoji, K.; Kimura, K.;

1996 / IEEE / 0-7803-3342-X

Description

This item was taken from the IEEE Periodical ' A 7.03-/spl mu/m/sup 2/ Vcc/2-plate nonvolatile DRAM cell with a Pt/PZT/Pt/TiN capacitor patterned by one-mask dry etching ' A ferroelectric memory cell with an area of only 7.03 /spl mu/m/sup 2/ designed with a 0.5-/spl mu/m rule has been fabricated. It performs Vcc/2-plate nonvolatile DRAM operation: ordinary DRAM operation and automatic nonvolatile writing when Vcc is shut down. A non-separated plate electrode and a capacitor patterned by one-mask dry etching reduce cell area. Planarization of the poly-Si plugs and the use of H-less metallization/passivation processes retain the PZT capacitor characteristics (Pr=50 fC/bit) and achieves ferroelectric write/read under /spl plusmn/2.5-V operation in 4-K bit memory cell arrays.