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A 2.7 V only 8 Mb/spl times/16 NOR flash memory
By: Akaogi, T.; Kuo, T.H.; Chen, J.C.; Kasa, Y.; Cleveland, L.E.; Kim, Y.K.; Leong, N.; Chung, C.K.;
1996 / IEEE / 0-7803-3339-X
This item was taken from the IEEE Periodical ' A 2.7 V only 8 Mb/spl times/16 NOR flash memory ' This paper describes a 80 ns, 2.7 V to 3.6 V single voltage supply 8 Mb/spl times/16 flash memory. It uses a high speed Vcc detector to control the wordline boost level and an intelligent programming algorithm to optimize the program time. Erase is achieved by a new low Vcc negative charge pump. The device is fabricated using a 0.5 /spl mu/m design rule, double layer metal, dual layer polysilicon, and triple well CMOS. The single transistor cell size is 1.7/spl times/1.7 /spl mu/m/sup 2/. The memory cell uses a conventional drain side channel hot electron for programming and negative gate Fowler-Nordheim tunneling on the source side for erase.
Nor Flash Memory
High Speed Vcc Detector
Wordline Boost Level Control
Intelligent Programming Algorithm
Negative Charge Pump
Double Layer Metal
Dual Layer Polysilicon
Triple Well Cmos Process
Drain Side Channel Hot Electron Programming
Negative Gate Fowler-nordheim Tunneling
2.7 To 3.6 V
Cmos Memory Circuits
Single Voltage Supply