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A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators

By: Matsuzaki, N.; Mizuno, H.; Kure, T.; Ishibashi, K.; Ishida, H.; Ooki, N.; Shinbo, T.; Osada, K.;

1996 / IEEE / 0-7803-3136-2

Description

This item was taken from the IEEE Periodical ' A 1 V 100 MHz 10 mW cache using separated bit-line memory hierarchy and domino tag comparators ' This cache operates at 10 mW, and 100 MHz at 1 V supply using separated bit-line memory hierarchy architecture (SBMHA) that reduces latency and power, and domino tag comparators (DTCs) that reduce dissipation of tag comparisons. On-chip caches in low-power microprocessors need high bit-ratio to reduce power. Higher bit-ratio is achieved using a larger cache. But this has the drawback of longer latency. The SBMHA hides the long latency.