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A novel CMP method for cost-effective bonded SOI wafer fabrication
By: Lee, B.H.; Shim, T.E.; Park, K.C.; Lee, K.W.; Yu, S.I.; Lee, J.H.; Kang, C.J.;
1995 / IEEE / 0-7803-2547-8
This item was taken from the IEEE Periodical ' A novel CMP method for cost-effective bonded SOI wafer fabrication ' The BOnded Silicon On Insulator (BOSOI) has been considered as a promising substitute for bulk silicon technology because of its structural flexibility. However,there are considerable drawbacks if epitaxial etch stopping or localized plasma etching technique is used in the fabrication process because of low throughput and high cost. In order to obtain the ultrathin SOI layer with uniform thickness, this paper describes the cost-effective fabrication method of bonded SOI wafer using the double step CMP method in which the abrasive concentration of slurry is controlled to enhance the polish throughput. In this technique, a low total thickness variation (TTV) wafer is used as a handle wafer and the thickness variation of SOI layer can be easily reduced within a reasonable polishing time if the abrasive concentration of slurry is properly adjusted.
Double Step Method
Silicon On Insulator Technology
Total Thickness Variation
Bonded Soi Wafer Fabrication