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A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing

By: Ishibashi, K.; Tachibana, S.; Kawasaki, I.; Yamamoto, M.; Yoshioka, S.; Matsui, S.; Izawa, R.; Kudoh, I.; Narita, S.; Hirose, K.; Nakazawa, T.; Uchiyama, K.; Nishimoto, J.; Shimazaki, Y.; Norisue, K.;

1995 / IEEE / 0-7800-2599-0

Description

This item was taken from the IEEE Periodical ' A low-power single-chip microprocessor with multiple page-size MMU for nomadic computing ' A low-power single-chip RISC microprocessor has been designed. It based on Hitachi's SH architecture with multiple page-size MMU. An automatic-power-save cache memory reduces the power dissipation at low frequencies, Two low-power modes and a module-stop function are software programmable for system power management. MMU supports 4 KB and 1 KB page-sizes by 4-way set-associative TLB. The chip using 0.5 um CMOS technology is fabricated, and achieves 60 Dhrystone MIPS and keeps 600 mW (max.), 60 MHz at worst condition.