Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM

By: Iwata, Y.; Imamiya, K.; Miyamoto, J.; Masuda, K.; Narita, K.; Nakamura, H.; Sugiura, Y.; Watanabe, T.; Ito, Y.; Momodomi, M.; Oodaira, H.; Araki, H.;

1995 / IEEE / 0-7803-2495-1


This item was taken from the IEEE Periodical ' A 35 ns-cycle-time 3.3 V-only 32 Mb NAND flash EEPROM ' A 32 Mb NAND type flash EEPROM in 0.425 /spl mu/m CMOS achieves 35 ns cycle time for data read-out and programming data load by adopting a pipeline scheme. Metal-strapped select gates and boosted word line reduce read-out access time. Tight-programmed cell Vth distribution can be realized by program verify, using a simplified data register circuit. Multiple blocks can be erased at the same time by adopting erase block registers for each block. Simultaneous-erase verify for one block reduces total erase time. All funtions require only 3.3 V power supply.