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Physical model of bit-to-bit variation in data retention time of DRAMs
By: Yanagisawa, Y.; Muranaka, M.; Ito, Y.; Ogasawara, M.; Tadaki, Y.; Miyai, Y.; Nagata, T.; Natsuaki, N.;
1995 / IEEE / 0-7803-2788-8
This item was taken from the IEEE Periodical ' Physical model of bit-to-bit variation in data retention time of DRAMs ' The low power application of DRAMs requires longer data retention time. Since the p-n junction current leakage is the main cause of the cell capacitor discharge, the leakage should be minimized to meet the requirement. However, the leakage taking place in a small area varies from bit to bit. Therefore, it is necessary to clarify the mechanism of the variation for the leakage minimization. A physical model, based on newly obtained experimental results, is proposed wherein the leakage variation is mainly due to a variation of local electric field strength enhancement.
P-n Junction Current Leakage
Cell Capacitor Discharge
Random Access Memory
Solid State Circuits
Data Retention Time
Local Electric Field Strength Enhancement
Integrated Circuit Measurement
Integrated Circuit Modelling
Integrated Circuit Reliability