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Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs
By: Saito, K.; Ishii, H.; Kamoshida, K.; Ito, Y.; Sakuma, K.; Yamamoto, E.; Amazawa, T.; Arita, Y.; Takeda, T.; Ueki, T.; Ikeda, K.; Hiraoka, K.; Yagi, S.; Kato, S.;
1995 / IEEE / 0-7803-2700-4
This item was taken from the IEEE Periodical ' Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs ' The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 /spl mu/m, equal pitch, four-level interconnection.
Gate Array Lsis
Chemical Mechanical Polishing
Selective Al Cvd Via Plugs
Ti/tin/ti Barrier Layers
Low Via Resistance
Equal Pitch Four-level Interconnection
Indium Tin Oxide
Large Scale Integration
Fully Planarized Four-level Interconnection System
Cmos Digital Integrated Circuits
Integrated Circuit Reliability
Integrated Circuit Interconnections