Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs

By: Saito, K.; Ishii, H.; Kamoshida, K.; Ito, Y.; Sakuma, K.; Yamamoto, E.; Amazawa, T.; Arita, Y.; Takeda, T.; Ueki, T.; Ikeda, K.; Hiraoka, K.; Yagi, S.; Kato, S.;

1995 / IEEE / 0-7803-2700-4

Description

This item was taken from the IEEE Periodical ' Fully planarized four-level interconnection with stacked vias using CMP of selective CVD-Al and insulator and its application to quarter micron gate array LSIs ' The chemical mechanical polishing (CMP) of selective aluminum (Al) CVD via plugs is examined for the first time and a fully planarized four-level interconnection system with all stacked via plugs is demonstrated. A sandwich of Ti/TiN/Ti barrier layers with an Al-CVD plug has proved to be one of the best via plug structures because of its low via resistance and extremely high reliability. Quarter-micron 120-kG gate array LSIs have been successfully fabricated using a 1.4 /spl mu/m, equal pitch, four-level interconnection.