Your Search Results

Use this resource - and many more! - in your textbook!

AcademicPub holds over eight million pieces of educational content for you to mix-and-match your way.

Experience the freedom of customizing your course pack with AcademicPub!
Not an educator but still interested in using this content? No problem! Visit our provider's page to contact the publisher and get permission directly.

An automatic-power-save cache memory for low-power RISC processors

By: Nagata, S.; Tamaki, S.; Yoshioka, S.; Izawa, R.; Kudoh, I.; Nakazawa, T.; Kawasaki, I.; Uchiyama, K.; Narita, S.; Norisue, K.; Ishibashi, K.; Shimazaki, Y.; Kuroda, K.;

1995 / IEEE / 0-7803-3036-6

Description

This item was taken from the IEEE Periodical ' An automatic-power-save cache memory for low-power RISC processors ' A test chip was fabricated using 0.5-/spl mu/m CMOS technology and the cache memory operated at 60 MHz with a supply voltage of 3.3 V, and it operated with a power dissipation of 8 mW with a supply voltage of 2.5 V at 10 MHz. Automatic-power-save architecture, a pulsed word technique and an isolated bit line technique reduced the power dissipation of the cache memory to almost 60% at a frequency of 60 MHz and to 20% at 10 MHz by these techniques.