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Architectural support for performance tuning: a case study on the SPARCcenter 2000

By: Singhal, A.; Goldberg, A.J.;

1994 / IEEE / 0-8186-5510-0

Description

This item was taken from the IEEE Periodical ' Architectural support for performance tuning: a case study on the SPARCcenter 2000 ' Latency hiding techniques such as multilevel cache hierarchies yield high performance when applications map well onto hierarchy implementations, but performance can suffer drastically when they do not. Identifying and reducing mismatches between an application and the memory hierarchy is difficult without insight into the actual behavior of the hardware implementation. The authors advocate the use of hardware event counters, as a cheap, effective and practical way to tune applications for a given hardware platform. They take a case study approach, focussing on the counters available on the SPARCcenter 2000, a 20 processor, shared-bus based multiprocessor. They describe the tools built to relate hardware event counts to user applications and give examples to illustrate how these tools are useful in practice. They conclude with a critique of the current hardware counters, offering a user's perspective on how they could be redesigned to be more effective.<>