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A 500 MHz 32b 0.4 /spl mu/m CMOS RISC processor LSI

By: Yamashina, M.; Nakayama, T.; Yamada, H.; Yano, Y.; Ono, A.; Okabe, K.; Abiko, H.; Koseki, Y.; Suzuki, K.; Inoue, T.; Goto, J.; Heiuchi, H.; Igura, H.; Nomura, M.; Izumikawa, M.;

1994 / IEEE / 0-7803-1844-7

Description

This item was taken from the IEEE Periodical ' A 500 MHz 32b 0.4 /spl mu/m CMOS RISC processor LSI ' This 500 MHz, 32b, reduced-instruction-set-computer (RISC) microprocessor uses 0.4 /spl mu/m CMOS technology. The microprocessor has an 8-stage pipelined data path. The 8 pipeline stages are: (1) instruction fetch 1 (I1); (2) instruction fetch 2 (I2); (3) register file fetch and instruction decode (RF); (4) execution 1 (E1); (5) execution 2 (E2); (6) data memory access 1 (D1); (7) data memory access 2 (D2); and (8) register file write-back (WB). The microprocessor includes a 32w/spl times/32b two-read/one-write register file, two double-stage pipelined 1 kB caches for both instructions and data, a 32b double-stage pipelined adder and barrel shifter, and a phase-locked loop circuit (PLL). The PLL multiplies input clock frequency by 2, 4 or 8 to obtain a 500 MHz internal clock.<>