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The next-generation SPARC multiprocessing system architecture

By: Cekleov, M.; Frailong, J.-M.; Singhal, A.; Price, J.; Splain, M.; Gastinel, J.; Sindhu, P.;

1993 / IEEE / 0-8186-3400-6

Description

This item was taken from the IEEE Periodical ' The next-generation SPARC multiprocessing system architecture ' The SPARCcenter 2000's multiprocessor architecture defines a set of functional building blocks that share a common hardware interface, the XDBus. This modular approach permits the implementation of multiprocessors covering a wide range of performance and cost. It allows the ratio of processing power, memory capacity, and I/O bandwidth to be varied within a given machine while permitting system designers to address different points on the overall performance spectrum. Each functional block (processor, memory, I/O) consists of a small number of highly integrated chips. The architecture provides a number of features to support high-performance symmetric multiprocessor software. These include hardware caches, TLB coherency, dynamic interrupt dispatching with source identification, weak write ordering, block copy hardware, and hardware performance monitoring.<>